library verilog;
use verilog.vl_types.all;
entity cmsdk_apb_slave_mux is
    generic(
        PORT0_ENABLE    : integer := 1;
        PORT1_ENABLE    : integer := 1;
        PORT2_ENABLE    : integer := 1;
        PORT3_ENABLE    : integer := 1;
        PORT4_ENABLE    : integer := 1;
        PORT5_ENABLE    : integer := 1;
        PORT6_ENABLE    : integer := 1;
        PORT7_ENABLE    : integer := 1;
        PORT8_ENABLE    : integer := 1;
        PORT9_ENABLE    : integer := 1;
        PORT10_ENABLE   : integer := 1;
        PORT11_ENABLE   : integer := 1;
        PORT12_ENABLE   : integer := 1;
        PORT13_ENABLE   : integer := 1;
        PORT14_ENABLE   : integer := 1;
        PORT15_ENABLE   : integer := 1
    );
    port(
        DECODE4BIT      : in     vl_logic_vector(3 downto 0);
        PSEL            : in     vl_logic;
        PSEL0           : out    vl_logic;
        PREADY0         : in     vl_logic;
        PRDATA0         : in     vl_logic_vector(31 downto 0);
        PSLVERR0        : in     vl_logic;
        PSEL1           : out    vl_logic;
        PREADY1         : in     vl_logic;
        PRDATA1         : in     vl_logic_vector(31 downto 0);
        PSLVERR1        : in     vl_logic;
        PSEL2           : out    vl_logic;
        PREADY2         : in     vl_logic;
        PRDATA2         : in     vl_logic_vector(31 downto 0);
        PSLVERR2        : in     vl_logic;
        PSEL3           : out    vl_logic;
        PREADY3         : in     vl_logic;
        PRDATA3         : in     vl_logic_vector(31 downto 0);
        PSLVERR3        : in     vl_logic;
        PSEL4           : out    vl_logic;
        PREADY4         : in     vl_logic;
        PRDATA4         : in     vl_logic_vector(31 downto 0);
        PSLVERR4        : in     vl_logic;
        PSEL5           : out    vl_logic;
        PREADY5         : in     vl_logic;
        PRDATA5         : in     vl_logic_vector(31 downto 0);
        PSLVERR5        : in     vl_logic;
        PSEL6           : out    vl_logic;
        PREADY6         : in     vl_logic;
        PRDATA6         : in     vl_logic_vector(31 downto 0);
        PSLVERR6        : in     vl_logic;
        PSEL7           : out    vl_logic;
        PREADY7         : in     vl_logic;
        PRDATA7         : in     vl_logic_vector(31 downto 0);
        PSLVERR7        : in     vl_logic;
        PSEL8           : out    vl_logic;
        PREADY8         : in     vl_logic;
        PRDATA8         : in     vl_logic_vector(31 downto 0);
        PSLVERR8        : in     vl_logic;
        PSEL9           : out    vl_logic;
        PREADY9         : in     vl_logic;
        PRDATA9         : in     vl_logic_vector(31 downto 0);
        PSLVERR9        : in     vl_logic;
        PSEL10          : out    vl_logic;
        PREADY10        : in     vl_logic;
        PRDATA10        : in     vl_logic_vector(31 downto 0);
        PSLVERR10       : in     vl_logic;
        PSEL11          : out    vl_logic;
        PREADY11        : in     vl_logic;
        PRDATA11        : in     vl_logic_vector(31 downto 0);
        PSLVERR11       : in     vl_logic;
        PSEL12          : out    vl_logic;
        PREADY12        : in     vl_logic;
        PRDATA12        : in     vl_logic_vector(31 downto 0);
        PSLVERR12       : in     vl_logic;
        PSEL13          : out    vl_logic;
        PREADY13        : in     vl_logic;
        PRDATA13        : in     vl_logic_vector(31 downto 0);
        PSLVERR13       : in     vl_logic;
        PSEL14          : out    vl_logic;
        PREADY14        : in     vl_logic;
        PRDATA14        : in     vl_logic_vector(31 downto 0);
        PSLVERR14       : in     vl_logic;
        PSEL15          : out    vl_logic;
        PREADY15        : in     vl_logic;
        PRDATA15        : in     vl_logic_vector(31 downto 0);
        PSLVERR15       : in     vl_logic;
        PREADY          : out    vl_logic;
        PRDATA          : out    vl_logic_vector(31 downto 0);
        PSLVERR         : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of PORT0_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT1_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT2_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT3_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT4_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT5_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT6_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT7_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT8_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT9_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT10_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT11_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT12_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT13_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT14_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT15_ENABLE : constant is 1;
end cmsdk_apb_slave_mux;
